Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the microelectronic industry for the fabrication of microelectronic devices. As these goals are achieved, the microelectronic devices scale down, i.e. become smaller, which increases the need for optimal performance from each integrated circuit component, including managing transistor drive currents while reducing short-channel effects, parasitic capacitance, and off-state leakage.
Non-planar transistors, such as fin and nanowire-based devices, enable improved control of short channel effects. For example in nanowire-based transistors, the gate electrode wraps around the full perimeter of the nanowire, enabling fuller depletion in the channel region, and reducing short-channel effects due to steeper sub-threshold current swing (SS) and smaller drain induced barrier lowering (DIBL). Wrap-around gate structures and source/drain contacts used in nanowire devices also enable greater management of leakage and capacitance in the active regions, even as drive currents increase, as will be understood to those skilled in the art.